The present invention relates to a hybrid integrated circuit in which a plurality of integrated circuits are mounted.
In recent years, an increase in integration degree and operation speed of LSIs has been remarkably high, and multi-pin chips that operate at a clock frequency of 100 MHz or more have become commercially available. In a single chip-mounted package of such a high-speed chip, a delay in signal transmitted between the package and the printed circuit board is large, and the influence of parasitic capacitance or inductance of the package cannot be neglected in system design. Signal delay, and the influences of the parasitic capacitance and inductance, interfere with an increase in operation speed of the entire system.
In order to increase the operation speed of the system by solving the above problems, a technique called a hybrid integrated circuit (multi-chip module: MCM) is available. According to the MCM, chips are arranged as close as possible to each other to decrease signal delay between chips caused by the package, and the high operation speed of a single chip can be obtained even in a system composed of a plurality of chips.
FIG. 6 shows the arrangement of the MCM. The arrangement of the MCM will be described. A wiring layer 603 is formed on a die pad 601a on a lead frame 601 through an insulating layer 602, and an upper wiring layer 605 is formed on the wiring layer 603 through an interlevel insulating film 604. An integrated circuit chip 606 and a resistor chip 607 are mounted at predetermined positions on the upper wiring layer 605. The integrated circuit chip 606 is connected to predetermined portions of the upper wiring layer 605 through wires 608. The predetermined portions of the upper wiring layer 605 and leads 601b are connected to each other through wires 608a. The resultant lead frame 601 is encapsulated with a molding resin 609 with the distal ends of the leads 601b being exposed.
In the conventional MCM described above, the ground wiring layers to be connected to the respective hybrid-packaged integrated circuit chips are formed in the wiring layer 603 shown in FIG. 6. The ground wiring layers formed in the wiring layer 603 are connected to electrodes formed on the upper wiring layer 605 at portions close to the edge of the die pad 601a through the interlevel insulating film 604, and the electrodes are connected to predetermined leads by using wires.
In the wiring layer 603 formed with the ground wiring layers, a large number of wiring layers are naturally formed which pose a problem in connection of the ground wiring layers. Therefore, conventionally, the ground wiring layers described above must be bypassed in the wiring layer 603 in a very complicated manner, and the number of hybrid-packaged integrated circuit chips cannot accordingly be increased.
It is, therefore, an object of the present invention to further increase the integration degree of the MCM.
In order to achieve the above object, according to the present invention, there is provided a hybrid integrated circuit comprising a metal substrate, a wiring structure comprised of a wiring layer formed on an upper surface of the substrate through an insulating layer, an integrated circuit chip arranged on the wiring structure and connected to a predetermined portion of the wiring structure, and a terminal arranged near the substrate to be insulated and isolated from the substrate and connected to the predetermined portion of the wiring structure, wherein the insulating layer has an extending connecting portion extending from the wiring structure to be connected to the substrate, and a fixed potential is connected to the integrated circuit chip through the extending connecting portion and the substrate.